KLC S4.3

Rules for pin stacking

Many symbols have corresponding footprints where multiple physical pins are connected to a single logical net. It is desirable that in such cases the user only has to connect a single pin in the schematic, and it will automatically route to all the physical pins on the PCB. (This is not only done to reduce clutter in the schematic drawing. The main reason is to move some responsibility for correct connections from the circuit designer over to the library.)

KiCad currently has no native method for designating that a particular symbol pin maps to multiple footprint pins. The following guide serves as a workaround for designing such symbols.

In the schematic view, pins that share the same position are considered to be connected by the KiCad routing algorithm. Thus, pins can only be placed in the same location under a very specific set of circumstances:

  1. Pins must not be of type No Connect (these pins should never be connected together)

  2. Power supply pins must be stacked unless the datasheet specifies the need for decoupling capacitors on every pin.

  3. Pins are logically connected in the symbol

  4. Pins must have the same name

  5. Pins must have the same electrical type

  6. One pin in the stack must be visible (all other pins set to invisible)

Special Case: Pins of electrical type [Output, Power Output, Power Input] are special cases.

  1. Connecting Output or Power Output pins would result in an ERC error. Output pins that always need to be connected together must therefore be stacked. The invisible pins get the pin type passive in this case.

  2. Invisible Power Input pins are global labels. This is to be avoided. For this reason the electrical type passive is to be used for the invisible pins in such stacks.

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