KLC S4.3

Rules for pin stacking

Many symbols have corresponding footprints where multiple physical pins are connected to a single logical net. It is desirable that in such cases the user only has to connect a single pin in the schematic, and it will automatically route to all the physical pins on the PCB.

KiCad currently has no native method for designating that a particular symbol pin maps to multiple footprint pins. The following guide serves as a workaround for designing such symbols.

In the schematic view, pins that share the same position are considered to be connected by the KiCad routing algorithm. Thus, pins can only be placed in the same location under a very specific set of circumstances:

  1. Pins must not be of type No Connect (these pins should never be connected together)

  2. Pins are logically connected in the symbol

  3. Pins must have the same name

  4. Pins must have the same electrical type

  5. One pin in the stack must be visible (all other pins set to invisible)

Special Case: Pins of electrical type [Output, Power Output, Power Input] are special cases. Connecting these pins together causes ERC (electrical rule check) errors and must be avoided.

For pin stacks using these pin types:

  1. Visible pin must be set to correct electrical type

  2. All invisible pins must have electrical type set to Passive

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